This section allows you to configure the system based on the specific features of the installed chipset. This chipset manages bus speeds and access to system memory resources, such as DRAM and the external cache. It also coordinates communications between the conventional ISA bus and the PCI bus.
The first chipset settings deal with CPU access to dynamic random access memory (DRAM).
DRAM must continually be refreshed or it will lose its data. Normally, DRAM is refreshed entirely as the result of a single request. Enabling this option allows DRAM to be refreshed in a sequence of four short bursts occurring at 1/4 cycles.
Disabled DRAM refreshes occur as single requests.
Enabled DRAM refreshes occur as four bursts at 1/4
cycle each.
Asserted DRAM RAS# will be asserted after every DRAM
cycle.
Deassert DRAM RAS# will be deasserted after every
DRAM cycle making each DRAM cycle a "Row
miss".
The cache DRAM controller offers two refresh modes, Normal and Hidden. In both modes, CAS takes place before RAS but the Normal mode requires a CPU cycle for each. On the other hand, a cycle is eliminated by "hiding" the CAS refresh in Hidden mode. Not only is the Hidden mode faster and more efficient, but it also allows the CPU to maintain the status of the cache even if the system goes into a power management "suspend" mode.
Normal DRAM refresh using normal CPU
cycles
Hidden DRAM refresh without CPU cycle for
CAS
This allows DRAM read and write bursts to have their timings coordinated.
X444/X444 Both read and write DRAM timings are
X-4-4-4
X444/X333 Read timing = X-4-4-4, write timing =
X-3-3-3
X333/X333 Both read and write DRAM timings are
X-3-3-3
Write buffers are hardware features which improve the overall system performance by allowing the processor (or bus master) to continue its current execution without writing data to its final destination. The data is temporairily stored in fast buffers. The cache-DRAM controller contains three types of write buffers:
1. CPU to DRAM
2. CPU to PCI Bus
3. PCI to DRAM
Enabled Data will be cached in a fast
buffer and CPU will not be
interrupted
Disabled Data will be written directly to
DRAM and the CPU will be
interrupted to control the write
operation.
When enabled, up to four Dwords of data can be sent to the PCI bus without interrupting the CPU. When disabled, a write buffer is not used and the CPU write cycle will not be completed until the PCI bus signals that it is ready to receive the data.
Enabled CPU writes are buffered, more data
is written and the system operates
faster.
Disabled CPU writes are not buffered and the
CPU is interrupted.
If enabled, a pair of buffers, with a capacity of four Dwords each, are used to store data written from the PCI bus to memory. When disabled, PCI writes to DRAM are limited to a single transfer.
Enabled PCI to DRAM writes are buffered Disabled PCI to DRAM writes are not buffered
Disabled is the default.
When enabled, the PCI bus will interpret CPU write cycles as the PCI burst protocol. This means that back-to-back sequential CPU memory write cycles addressed to the PCI will be translated into the fast PCI burst memory write cycles. This will directly improve the video performance when consecutive writes are initiated to a linear graphics frame buffer.
Enabled PCI burst protocol used for
successive PCI memory writes.
Disabled Conventional write cycles are used.
Disabled is the default.
CAS means Column Address Strobe. When DRAM is read from, written to or refreshed, the memory is addressed in terms of its column and row position. Enabling an extra wait for the CAS means that reads, writes or refreshes will take slightly longer.
Enabled An extra wait state is used for CAS
Disabled No additional wait state used for
CAS
Disabled is the default.
RAS means Row Address Strobe. When DRAM is read from, written to or refreshed, the memory is addressed in terms of its column and row position. Enabling an extra wait for the RAS means that reads, writes or refreshes will take slightly longer.
Enabled An extra wait state is used for RAS
Disabled No additional wait state used for
RAS
Disabled is the default.
When enabled, accesses to the system BIOS ROM addressed at F0000H-FFFFFH are cached, provided that the cache controller is enabled.
Enabled BIOS access cached Disabled BIOS access not cached
As with caching the System BIOS above, enabling the Video BIOS cache will cause access to video BIOS addressed at C0000H to C7FFFH to be cached, if the cache controller is also enabled,
Enabled Video BIOS access cached Disabled Video BIOS access not cached
The wait state is typically a function of the speed of the external cache. For a slower cache, disabling the L2 Cach Zero Wait State will cause the chipset to assert one wait state when accessing the external cache controller. When enabled, the chipset will not wait.
Enabled Zero wait state Disabled One wait state
When enabled, this allows data sent from the CPU to the PCI bus to be held in a buffer. The chipset will then write the data in the buffer to the PCI bus when appropriate.
Enabled CPU-TO-PCI writes are buffered Disabled Writes NOT buffered
When enabled, this allows the chipset to apply features like "CPU-TO-PCI Byte Merge", "CPU-TO-PCI Prefetch" to be applied to VGA memory range A0000H-BFFFFH.
Enabled VGA receives CPU-TO-PCI functions Disabled Retain standard VGA interface.
In order to improve performance, certain space in memory is reserved for ISA cards. This memory must be mapped into the memory space below 16 MB. The user defined start address is the beginning address of this space.
The selections are from 1 to 15 with each number in MB. This selection will have no meaning if the memory hole is "disabled" (see below).
This allows the user to define the size of the memory hole reserved for ISA cards. The options are "disabled", 64KB, 126KB, 256KB, 1MB, 2MB, 4MB, 8MB.
This should be Enabled if a PCI SCSI controller is installed on the motherboard. This allows the PCI controller to scan the SCSI ROM. This should be Disabled if the SCSI controller is absent.
Enabled PCI SCSI controller installed Disabled PCI SCSI controller not installed
This is the length of time in seconds the BIOS will wait for the SCSI hard disk to be ready for operation. If the hard drive is not ready, the PCI SCSI BIOS might not detect the hard drive correctly.
The range of selections is from 0-60 seconds.
This section describes configuring the PCI bus system. PCI, or Personal Computer Interconnect, is a system which allows I/O devices to operate at speeds nearing the speed the CPU itself uses when communicating with its own special components. This section covers some very technical items and it is strongly recommended that only experienced users should make any changes to the default settings.
Since the PCI bus is operating at a speed much greater than a standard ISA bus, the PCI bus must be delayed when interacting with the standard bus. The Latency Timer feature allows the you to define how long the PCI bus will delay. This number is dependent on the PCI master device in use and varies as a fraction of the PCI bus clock rate.
Each PCI slot must get the attention of the PCI controller when it wants to perform some I/O. The PCI bus supports interrupts A, B, C and D. Each time one of this interrupts is generated a request is signaled to and handled by the PCI bus. However, since the operating system usually has the final responsibility for handling I/O, these interrupts can be associated with an IRQ if the device occupying a given slot requires an IRQ service.
This feature allows you to define the time delay for data movements between the PCI SCSI controller and the slower standard bus. The units are clock ticks of the PCI clock operating at 33mhz.
This allows you to select an interrupt for the NCR PCI 53C810 controller.
You can select which PIRQ is associated with each PCI slot and which conventional IRQ is associated with with PIRQ. The IRQ settings must be the same as the jumper settings on the motherboard.
A setting of NA means the IRQ has been assigned to the ISA bus and is not available to any PCI slot.