This section allows you to configure the system based on the specific features of the installed chipset. This chipset manages bus speeds and access to system memory resources, such as DRAM and the external cache. It also coordinates communications between the conventional ISA bus and the PCI bus
The first chipset settings deal with CPU access to dynamic random access memory (DRAM).
DRAM must continually be refreshed or it will lose its data. Normally, DRAM is refreshed entirely as the result of a single request. Enabling this option allows DRAM to be refreshed in a sequence of four short bursts occurring at 1/4 cycles.
Disabled DRAM refreshes occur as single requests.
Enabled DRAM refreshes occur as four bursts at 1/4
cycle each.
Asserted DRAM RAS# will be asserted after every DRAM
cycle.
Deassert DRAM RAS# will be deasserted after every
DRAM cycle making each DRAM cycle a "Row
miss".
The cache DRAM controller offers two refresh modes, Normal and Hidden. In both modes, CAS takes place before RAS but the Normal mode requires a CPU cycle for each. On the other hand, a cycle is eliminated by "hiding" the CAS refresh in Hidden mode. Not only is the Hidden mode faster and more efficient, but it also allows the CPU to maintain the status of the cache even if the system goes into a power management "suspend" mode.
Normal DRAM refresh using normal CPU
cycles
Hidden DRAM refresh without CPU cycle for
CAS
This allows DRAM read and write bursts to have their timings coordinated.
X444/X444 Both read and write DRAM timings are
X-4-4-4
X444/X333 Read timing = X-4-4-4, write timing =
X-3-3-3
X333/X333 Both read and write DRAM timings are
X-3-3-3
Write buffers are hardware features which improve the overall system performance by allowing the processor (or bus master) to continue its current execution without writing data to its final destination. The data is temporairily stored in fast buffers. The cache-DRAM controller contains three types of write buffers:
1. CPU to DRAM
2. CPU to PCI Bus
3. PCI to DRAM
Enabled Data will be cached in a fast
buffer and CPU will not be
interrupted
Disabled Data will be written directly to
DRAM and the CPU will be
interrupted to control the write
operation.
When enabled, up to four Dwords of data can be sent to the PCI bus without interrupting the CPU. When disabled, a write buffer is not used and the CPU write cycle will not be completed until the PCI bus signals that it is ready to receive the data.
Enabled CPU writes are buffered, more data
is written and the system operates
faster.
Disabled CPU writes are not buffered and the
CPU is interrupted.
If enabled, a pair of buffers, with a capacity of four Dwords each, are used to store data written from the PCI bus to memory. When disabled, PCI writes to DRAM are limited to a single transfer.
Enabled PCI to DRAM writes are buffered Disabled PCI to DRAM writes are not buffered
Disabled is the default.
When enabled, the PCI bus will interpret CPU write cycles as the PCI burst protocol. This means that back-to-back sequential CPU memory write cycles addressed to the PCI will be translated into the fast PCI burst memory write cycles. This will directly improve the video performance when consecutive writes are initiated to a linear graphics frame buffer.
Enabled PCI burst protocol used for
successive PCI memory writes.
Disabled Conventional write cycles are used.
Disabled is the default.
CAS means Column Address Strobe. When DRAM is read from, written to or refreshed, the memory is addressed in terms of its column and row position. Enabling an extra wait for the CAS means that reads, writes or refreshes will take slightly longer.
Enabled An extra wait state is used for CAS
Disabled No additional wait state used for
CAS
Disabled is the default.
RAS means Row Address Strobe. When DRAM is read from, written to or refreshed, the memory is addressed in terms of its column and row position. Enabling an extra wait for the RAS means that reads, writes or refreshes will take slightly longer.
Enabled An extra wait state is used for RAS
Disabled No additional wait state used for
RAS
Disabled is the default.
When enabled, accesses to the system BIOS ROM addressed at F0000H-FFFFFH are cached, provided that the cache controller is enabled.
Enabled BIOS access cached Disabled BIOS access not cached
As with caching the System BIOS above, enabling the Video BIOS cache will cause access to video BIOS addressed at C0000H to C7FFFH to be cached, if the cache controller is also enabled,
Enabled Video BIOS access cached Disabled Video BIOS access not cached
The wait state is typically a function of the speed of the external cache. For a slower cache, disabling the L2 Cach Zero Wait State will cause the chipset to assert one wait state when accessing the external cache controller. When enabled, the chipset will not wait.
Enabled Zero wait state Disabled One wait state
When enabled, this allows data sent from the CPU to the PCI bus to be held in a buffer. The chipset will then write the data in the buffer to the PCI bus when appropriate.
Enabled CPU-TO-PCI writes are buffered Disabled Writes NOT buffered
When enabled, this allows the chipset to apply features like "CPU-TO-PCI Byte Merge", "CPU-TO-PCI Prefetch" to be applied to VGA memory range A0000H-BFFFFH.
Enabled VGA receives CPU-TO-PCI functions Disabled Retain standard VGA interface.
In order to improve performance, certain space in memory is reserved for ISA cards. This memory must be mapped into the memory space below 16 MB. The user defined start address is the beginning address of this space.
The selections are from 1 to 15 with each number in MB. This selection will have no meaning if the memory hole is "disabled" (see below).
This allows the user to define the size of the memory hole reserved for ISA cards. The options are "disabled", 64KB, 126KB, 256KB, 1MB, 2MB, 4MB, 8MB.
The Power Management Setup allows you to configure you system to most effectively save energy while operating in a manner consistent with your own style of computer use.
This category allows you to select the type (or degree) of power saving and is directly related to the following modes:
1. Doze Mode
2. Standby Mode
3. Suspend Mode
4. HDD Power Down
There are four selections for Power Management, three of which have fixed mode settings.
Disable (default) No power management. Disables all four
modes
Min. Power Saving Minimum power management. Doze Mode = 1
hr. Standby Mode = 1 hr., Suspend Mode = 1
hr., and HDD Power Down = 15 min.
Max. Power Saving Maximum power management -- ONLY AVAILABLE
FOR SL CPU'S. Doze Mode = 1 min., Standby
Mode = 1 min., Suspend Mode = 1 min., and
HDD Power Down = 1 min.
User Defined Allows you to set each mode individually.
When not disabled, each of the ranges are
from 1 min. to 1 hr. except for HDD Power
Down which ranges from 1 min. to 15 min.
and disable.
When enabled, an Advanced Power Management device will be activated to enhance the Max. Power Saving mode and stop the CPU internal clock.
If the Max. Power Saving is not enabled, this will be preset to No.
This determines the manner in which the monitor is blanked.
V/H SYNC+Blank This selection will cause the system to
turn off the vertical and horizontal
synchronization ports and write blanks to
the video buffer.
Blank Screen This option only writes blanks to the
video buffer.
The following four modes are Green PC power saving functions which are only user configurable when User Defined Power Management has been selected. See above for available selections.
When enabled and after the set time of system inactivity, the CPU clock will run at at slower speed while all other devices still operate at full speed.
When enabled and after the set time of system inactivity, the fixed disk drive and the video would be shut off while all other devices still operate at full speed.
When enabled and after the set time of system inactivity, all devices except the CPU will be shut off.
When enabled and after the set time of system inactivity, the hard disk drive will be powered down while all other devices remain active.
Power Down Activities events are I/O events whose occurrence can prevent the system from entering a power saving mode or can awaken the system from such a mode. In effect, the system remains alert for anything which occurs to a device which is configured as On, even when the system is in a power down mode.
When set to On (default), any event occurring at a COM (serial) port will awaken a system which has been powered down.
When set to On (default), any event occurring at a LPT (printer) port will awaken a system which has been powered down.
When set to On (default), any event occurring at a hard or floppy drive port will awaken a system which has been powered down.
When set to On (default), any event occurring at the keyboard will awaken a system which has been powered down.
The following is a list of IRQ's, Interrupt ReQuests, which can be exempted much as the COM ports and LPT ports above can. When an I/O device wants to gain the attention of the operating system, it signals this by causing an IRQ to occur. When the operating system is ready to respond to the request, it interrupts itself and performs the service.
As above, the choices are On and Off. Off is the default.
When set On, activity will neither prevent the system from going into a power management mode nor awaken it.
This section describes configuring the PCI bus system. PCI, or Personal Computer Interconnect, is a system which allows I/O devices to operate at speeds nearing the speed the CPU itself uses when communicating with its own special components. This section covers some very technical items and it is strongly recommended that only experienced users should make any changes to the default settings.
Some PCI devices use interrupts to signal that they need to use the PCI bus. Some devices, notably most graphics adapters, may not need an interrupt service at all. Each PCI slot is capable of activating up to four interrupts, INT# A, INT# B, INT# C and INT# D. By default, a PCI slot is allowed INT# A. Assigning INT# B has no meaning unless the device in the slot requires two interrupt services rather than just one. Likewise, using INT# C can only mean the device requires three interrupts and similarily for INT# D.
Selecting the default, AUTO, allows the PCI controller to automatically allocate the interrupts.
A INT# is an interrupt request which is signaled to and handled by the PCI bus. However, since the operating system usually has the final responsibility for handling I/O, INT#s can be mapped to an IRQ if the device occupying a given slot requires an IRQ service. By default, IRQ's 9 and 10 to PCI are mapped to PCI devices, but any available, unused IRQ can be used.
You can select which INT# is associated with each PCI slot and which conventional IRQ is associated with one of the two available INT#s. The IRQ settings must be the same as the jumper settings on the motherboard.
A setting of NA means the IRQ has been assigned to the ISA bus and is not available to any PCI slot.
This sets the method by which the PCI bus recognizes that an IRQ service is being requested by a device. Under all circumstances, you should retain the default configuration unless advised otherwise by your system's manufacturer.
Choices are Level (default) and Edge.
This allows you to configure your system to the type of IDE disk controller in use. By default, Setup assumes that your controller is an ISA (Industry Standard Architecture) device rather than a PCI controller. The more apparent difference is the type of slot being used.
If you have equipped your system with a PCI controller, changing this allows you to specify which slot has the controller and which PCI interrupt (A, B,C or D) is associated with the connected hard drives.
Remember that this setting refers to the hard disk drive itself, rather than individual partitions. Since each IDE controller supports two separate hard drives, you can select the INT# for each. Again, you will note that the primary has a lower interrupt than the secondary as described in "Slot x Using INT#" above.
Selecting "PCI Auto" allows the system to automatically determine how your IDE disk system is configured.