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Crossbrand - Memory products glossary
Applicable to: World-Wide
Asynchronous Operating mode in which a memory device responds to input signals whenever they occur. As opposed to synchronous operation in which the input signals must be present at specified times in the device's clock cycle.
Auto precharge A Synchronous DRAM (Dynamic Random Access Memory) feature that allows the memory chip's circuitry to close a page automatically at the end of a burst.
Auto refresh Commonly referred to as CAS (Column Address Select)\ before RAS (Row Address Select)\ refresh or CE before RE refresh. An internal address counter increments the row address each time the memory controller initiates a CAS\ before RAS\ refresh cycle.
BEDO Burst EDO (Extended Data Out) DRAM. An EDO DRAM with some burst features such as a four bit burst length that can be delivered in sequential or interleave fashion.
Block write A VRAM (Video RAM) feature that allows the user to write 8 columns per page cycle. Columns may be masked to permit partial writes.
Buffering Adding logic, particularly drivers, to a SIMM or DIMM (Dual Inline Memory Module) to increase the output current. Buffering is used to overcome signal attenuation due to capacitive loading.
Burst Multiple bits of data from a single device accessed in rapid succession. Burst lengths vary by product and user application.
Burst rate The rate at which data in a burst can be accessed. The burst rate is usually shown as the number of clock cycles required for each bit of data in a burst. For example, the burst rate for a 4-bit burst on an SRAM operating at microprocessor speed would be shown as 2/1/1/1 or two cycles for the first bit, and one additional cycle for each subsequent bit.
Byte-write A memory operation in which one or more bytes on a data bus are masked during a store operation so that only particular bytes are accessed and written to. Byte write may be used in SRAM and DRAM applications.
Cache A small amount of memory (usually SRAM) used to temporarily store data. Properly designed, a cache improves system performance by reducing the need to access the system's main memory for every transaction.
CAS Column Address Select. A control pin on a DRAM used to latch and activate a column address. The column selected on a DRAM is determined by the data present at the address pins when CAS becomes active.
Check bits Extra data bits provided by a DRAM module to support ECC function. For a 4-byte bus, 7 or 8 check bits are needed to implement ECC (Error Correction Code), resulting in a total bus width of 39 or 40 bits. On an 8-byte bus, 8 additional bits are required, resulting in a bus width of 72 bits.
DRAM DIMM Dual Inline Memory Module. DIMMs are small memory cards with data buses of 64, 72, or 80 bits. Unlike SIMMs, DIMMS have functionally unique contacts on the front and back of the card. Designed to meet JEDEC standards, DIMMs come with a variety of sizes, speeds, and features.
Dual clock operation In SRAMs, a means for controlling output timing independent of input timing using two clock signals.
ECC Error Correction Code. ECC is logic designed to correct memory errors. The number of errors that can be corrected depends upon the algorithms used, and the number of error correction bits (non-data bits) present. This logic may be included on a SIMM, or it may be found on one of the computer's circuit boards. Some systems do not have or need ECC
ECC on SIMM SIMMs, featuring on-board ECC logic, designed to be plug compatible with parity based SIMMs. The ECC logic corrects single errors in each byte of SIMM data.
ECC optimized On a SIMM or DIMM, the use of a module addressing architecture that facilitates the use of the memory module by systems with ECC. ECC optimized memory modules do not have byte-write capability.
EDO Extended Data Out. A DRAM performance feature that permits multiple bits of data in a single row to be accessed quickly. EDO involves selecting multiple column addresses in rapid succession once the row address has been selected. Once the first column address has been selected and CAS becomes active, the data output drivers are activated. The data output drivers remain active for each successive CAS strobe, until RAS goes high.
Flash write A VRAM feature that permits the user to clear an entire row at once. This feature is used to clear an entire buffer quickly.
Flow through In SRAMs, operation in which data is retrieved in a single memory cycle. Data bits that are read must be retrieved immediately or they will be lost.
FPM Fast Page Mode. A timing option that permits several bits of data in a single row on a DRAM to be accessed at an accelerated rate. Fast Page Mode involves selecting multiple column addresses in rapid succession once the row address has been selected. Each time a column address is selected and CAS becomes active, the data output drivers are activated; each time CAS goes high, the data output drivers are deactivated.
HER Hard Error Rate. The failure rate due to permanent or "hard" fails.
HPM Hyper Page Mode. In DRAM operation, another term for EDO or Extended Data Out.
Hi-Z A high impedance condition that cannot be interpreted as either a 1 or a 0 by system logic.
IC DRAM A small memory card that is completely enclosed in plastic or some other durable material. With dimensions similar to a PCMCIA card, the IC DRAM looks like a thick credit card.
ID Identification Detect. Pins present on DIMMs to provide bus size and self refresh information to the system using the module.
I2C interface A protocol that defines any device that puts data onto the bus as a transmitter and any device that reads the data on the bus as a receiver. The device that controls the data transfer is called the master; the device receives the data is the slave device. This protocol is used for the serial presence detect EEPROM used on some DIMMs.
Interleave The process of taking data bits (singly or in bursts) alternately from two or more memory pages (on an SDRAM) or devices (on a memory card or subsystem).
JEDEC An organization that establishes standards for memory operation, features, and packaging.
JTAG functions In SRAMs, industry defined functions used to test the interconnection between SRAM I/Os and printed circuit board traces or other components.
Keys Notches in a memory module (DRAM DIMM or SIMM) that prevent them from being plugged into an incompatible system. For example, a DIMM keyed for 3.3V operation cannot be plugged into a socket designed for use with a 5V system.
Late write In SRAMs, a feature that allows write data to be registered one clock cycle after the addresses and controls. This feature is used to eliminate the delay normally experienced when a read operation is followed by a write operation.
Low power A designation that implies that the DRAM chips used to make up the memory module have been designed with extended memory retention or self refresh capability, resulting in very low standby power supply current requirements.
OE Output Enable. A control pin on a DRAM that permits the user to enable or disable the data output drivers.
Page On a DRAM, the number of bits that can be accessed from one row address. The size of a page is determined by the number of column addresses. For example, a device with 10 column address pins has a page depth of 1024 bits.
Parity Logic that detects the presence of an error in memory. Generally, a single parity bit is used for each byte (8 bits) of data. The most commonly used forms of parity are even parity, odd parity, and checksums.
PD Presence Detect. Indicator pins on SIMMs and DIMMs that provide speed and density information to the system using the memory module.
Pipeline In DRAMs and SRAMs, a method for increasing the performance using multistage circuitry to stack or save data while new data is being accessed. The depth of a pipeline varies from product to product. For example, in an EDO DRAM, one bit of data appears on the output while the next bit is being accessed. In some SRAMs, pipelines may contain bits of data or more.
Precharge On a DRAM, the amount of time required between a control signal's (such as RAS) transition to an inactive state and its next transition to an active state.
RAS Row Address Select. A control pin on a DRAM used to latch and activate a row address. The row selected on a DRAM is determined by the data present at the address pins when RAS becomes active.
Refresh The process used to restore the charge in DRAM memory cells at specified intervals. The required refresh interval is a function of the memory cell design and the semiconductor technology used to manufacture the memory device. There are several refresh schemes that may be used.
SAM Serial Register/Serial Access Memory. A SAM is a serial register built into a VRAM to enable it to transfer large quantities of data from the DRAM portion of the device to a graphics controller or frame buffer. A full SAM is 512K x 16; a half SAM is 256K x 16.
SDRAM Synchronous Dynamic Random Access Memory or Synchronous DRAM. A DRAM designed to deliver bursts of data at very high speed using automatic addressing, multiple page interleaving, and a synchronous (or clocked) interface.
Self Refresh On an SDRAM, a form of refresh that allows the device to generate the control signals necessary to refresh storage cells within the allotted retention interval.
SER Soft Error Rate. The failure rate due to soft fails. Soft fails are fails caused by alpha particles or cosmic rays. They disappear once the memory is powered down and restarted.
Serial Presence Detect An enhanced presence detect system that uses a 256 byte serial EEPROM to store density, performance, and other manufacturer data. This function is provided on some DIMMs and SO DIMMs.
SGRAM Synchronous Graphics RAM. A single port DRAM designed for graphics applications that require high speed serial data.
SIMM Single Inline Memory Module. SIMMs are small memory cards with data buses of 32, 36, or 40 bits. SIMMs have functionally equivalent connections on both sides of the card. Designed to meet JEDEC standards, SIMMs come with a variety of sizes, speeds, and features.
Sleep mode In SRAMs, a mode that places the outputs in a high impedance state and reduces chip power consumption to standby levels.
Split Read/Write This VRAM function allows the user to split the SAM in half so that one half can be read from or written to while the other half is being loaded from the DRAM.
SO DIMM Small Outline Dual Inline Memory Module. SO DIMMs are narrower and thinner than standard DIMMs. This is achieved by using memory devices in TSOP packages.
SOJ Small Outline J-Lead package. This plastic package, designed for memory chips, is a surface mount package with turned under leads that look like the letter J.
SRS Serial Register Stop. This VRAM feature is a stop pointer used to read tiles of programmable width. It is used to divide the frame buffer into tiles of certain widths so that data can be written in page mode.
TSOP Thin Small Outline Package. This plastic package, designed for memory chips has approximately half the height of a standard surface mounted plastic package (SOJ).
UMA Unified Memory Architecture. Memory architecture in which main memory DRAM signals are shared by the system memory controller and the graphics controller.
VRAM Video RAM. DRAM with an on-board serial register/serial access memory designed for video applications. VRAM designs include a serial port for providing data to the CRT refresh circuitry and a parallel port for read/write data transfers from the graphics controller.
WPBM Writer Per Bit Mask. This VRAM feature permits the user to mask inputs to prevent the specified bits from being written. Persistent masks may be created using the Mask buffer. Non-persistent masks are created using the write per bit mask.
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Memory | |
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Date Created |
03-11-97 | |
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Last Updated |
27-08-98 | |
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Revision Date |
21-08-99 | |
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Brand |
IBM Aptiva, IBM ThinkPad | |
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Product Family |
Aptiva, PS/1, ThinkPads General | |
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Machine Type |
Various | |
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