THE PROGRAMMABLE LOGIC EXPLORER

Been wanting to experiment with programmable logic, but do not know
where to start? Well the PROGRAMMABLE LOGIC EXPLORER is for you! The
PROGRAMMABLE LOGIC EXPLORER is a small PC board that connects to your PC
through a printer port.  Everything you need (except a PC) to design,
program and test your programmable logic designs is included. 

At the core of the PROGRAMMABLE LOGIC EXPLORER is the Lattice
ispGAL22V10.  The ispGAL22V10 is a special version of the very popular
22V10 PLD (Programmable Logic Device).  The 22V10 has been an engineer
favorite for many years because of it's straight forward flexible
architecture, wide availability and low cost.  A standard 22V10 comes in
a 24 pin DIP package or a 28 pin PLCC package.  In the 28 pin PLCC
package, the 4 extra pins are not used.  The ispGAL22V10 is only
available in a 28 pin PLCC package, however the 4 pins that are normally
not used in a standard 22V10, are used to provide an in system
programming interface.  This means that the ispGAL22V10 can be
programmed without a standard programmer.  This capability is used by
the PROGRAMMABLE LOGIC EXPLORER to make an inexpensive programmable
logic design center. 

As shown in the schematic the ispGAL22V10's programming pins SCLK (pin
1), MODE (pin 8) and SDI (pin 22) are controlled by the DATA1, DATA2 and
DATA0 signals from the PC's printer port.  These signals are buffered
through 2 gates of a 74HCT14 hex inverter to give improved noise
immunity.  The remaining programming signal is SDO which is driven by
the ispGAL22V10. This signal is feed through 2 inverter gates into the
ACK* input signal on the printer port. The remaining printer port output
signals are connected (some though inverters) to the standard 22V10
input pins. Each of the ten 22V10 I/O signals are set up to drive LEDs,
the LED will turn on when the output is a logic low. The 7805 is used to
provide regulated 5 volt power to the ICs and LEDs from a nominal 9
volt DC, 200 milliamp, unregulated power supply input.

BUILDING THE PROGRAMMABLE LOGIC EXPLORER

Building the PROGRAMMABLE LOGIC EXPLORER is a very straight forward
operation.  It is best to build it on a double sided PC board with
plated through holes (check the parts list if you wish to purchase a PC
board or other parts kit).  It is always a good idea to verify power
supply operation BEFORE installing the ICs.  Check for +5 volts at U1
pin 14, U2 pin 14 and U3 pin 28 (reference the diagram for the PLCC
socket pin out).  The use of sockets for U1 and U2 are optional, U3 must
use a socket.  Once the ICs are installed and all solder joints have
been double checked the PROGRAMMABLE LOGIC EXPLORER is ready for use. 

TESTING THE PROGRAMMABLE LOGIC EXPLORER

To get started you will need the archive PLDXPLOR.ZIP.  You can download
PLDXPLOR.ZIP from the Alta Engineering Web site
(http://www.gutbang.com/alta) on the Internet or from several of the
BBSes listed in the resource list.  You can also order a disk containing
PLDXPLOR.ZIP and many other goodies from Alta Engineering, see the parts
list for details.  Once you have a copy of PLDXPLOR.ZIP, you should make
a directory PLDXPLOR on your hard drive, copy PLDXPLOR.ZIP into that
directory and then unzip the file.  This should produce a bunch of
files, including I22_PROG.EXE and PLDXPLOR.ISP that we'll use now. 
Connect the Programmable Logic Explorer to one of the PC's printer ports
using a DB25 male to male cable (all cable pins must be connected, pin1
to pin1, pin2 to pin2, and so on up to pin25).  Note whether you are
using LPT1 or LPT2.  Connect the 9 Volt power supply to the Programmable
Logic Explorer.  Then enter the command line:

I22_PROG PLDXPLOR.ISP n

where n is either 1 or 2 for the LPT port number that you are using. 
The program should indicate that it is erasing and then programming the
ispGAL22V10.  In less then a minute it should finish by verifying the
ispGAL22V10 and then your command prompt will return.  If there are any
error indications then try the other LPT number on the command line. 
Note that LPT1 is at address 378H and LPT2 at 278H.  If everything is
working so far we can test the rest of the Programmable Logic Explorer. 
Enter the command line:

XPLORVEC n

where n is either 1 or 2 for the LPT port number that you are using. 
XPLORVEC is a utility that allows you to control the signals applied to
8 of the ispGAL22V10 input pins.  Each time you press return the 0 or 1
signal level is applied to the corresponding pin.  The display shows the
pin numbers 10, 9, 7, 6, 5, 4, 3 and 2 above the signal levels (0 or 1). 
The signal levels should be initially all 0.  Press ENTER to apply the
0's to the input pins.  The bottom 8 LEDs should all be lit and the top
two should be off.  The cursor should be under the label for pin 10. 
Press the 1 key, the value under the 10 should turn to 1 and the cursor
will move to under the 9.  Press ENTER and the third LED from the top
should go off.  Pin by pin, turn the signal level from a 0 to 1 and
press ENTER.  Each successive LED should go off.  When the signal for
pin 3 is set to 1 then the top LED should go on.  When the signal for
pin 2 is set to 1 then the second LED from the top should go on.  If all
of the LEDs respond properly then the Programmable Logic Explorer is
fully functional.  Press ESC to exit XPLORVEC.  If there are any
problems trace the signal through to the input pins making sure that
they are toggled with proper logic levels (remember TTL 0 is less then
0.8 volts and 1 is greater then 2.4 volts).  If the input signals are OK
check the output signals to the LEDs.  Keep in mind that the LEDs will
go on when the output signal is low. 

USING THE PROGRAMMABLE LOGIC EXPLORER

To use the Programmable Logic Explorer you will need a logic compiler in
addition to the utilities in PLDXPLOR.ZIP.  There are three FREE logic
compilers that are suitable for use with the PROGRAMMABLE LOGIC
EXPLORER.  One is PLACE which is available from the ICT BBS.  The other
two are PLAN and OPAL Jr. which were made available by National
Semiconductor before they got out of the PLD business, these are
available off of many of the BBSes listed in the resources.  I will use
the PLAN/OPAL Jr. utilities in my examples. 

A logic compiler is a program that takes a design file as input and
produces a JEDEC file as output.  The design file is a standard ASCII
text file.  It describes the desired device pin out and the equations
for the internal logic to be implemented.  The JEDEC file is the file
that contains the programming information for the device and is the
standard file used by device programmers.  For our example we will use
the design file XPLORCNT.EQN.  This file implements the logic for two 5
bit counters.  Notice that the file is made up of two sections, the top
section is the DECLARATION.  In the declaration we give our design a
name (XPLORCNT), list the type of PLD we are using (22V10) and then
define our symbolic names for the pins.  The pin names are defined in
numerical order except that the programming pins (SCLK, SDO, MODE and
SDI are ignored).  In this case we've given pin 2 the name CLK and pin
27 the name QA etc.  The pins with the name NC are not used in this
case.  The lines that begin with a ; are comments.  The second section
starts with the keyword EQUATIONS and is naturally called the equation
section.  This section contains the logical equations for our design. 
In this case the equations define the two 5 bit counters.  From the
equation file we use the logic compiler to create a JEDEC file with the
following command line:

EQN2JED -N -J XPLORCNT

This creates the JEDEC file XPLORCNT.JED. The Programmable Logic
Explorer can not use the JEDEC file directly, the JEDEC must be
converted into an ISP file. This is done with the command line:

JEDTOISP XPLORCNT.JED XPLORCNT.ISP

The ISP file is now used to program the ispGAL22V10 on the Programmable
Logic Explorer with the command line:

I22_PROG XPLORCNT.ISP n

Where n is the LPT port number (1 or 2). The display should indicate
the erase, programming and verify operations. The ispGAL22V10 is
designed to handle a minimum of 10,000 programming operations. The
program is non-volatile, it retains it's program even when the power is
off, so you can remove the programmed device for use in another system.

Once programming is complete we can test our design using the XPLORVEC
utility.  In this case the only input pin that is used is pin 2, which
is used as the clock input.  On each 0 to 1 transition on pin 2 our
counters should increment 1 count.  You can move the cursor (use arrow
keys) all the way to the right under the signal for pin 2 and press 0
then ENTER and then 1 and ENTER. This toggles the signal to pin 2 and
will cause the counters to increment as shown by the LEDs. Since this is
a bit awkward, you have the option of pressing the C key when the cursor
is under the signal for pin 2. The C indicates that you want a CLOCK
pulse to appear at pin 2 on each ENTER. If you press enter you know see
the counters increment on each key press. By using XPLORVEC we can apply
test signals to the inputs of the ispGAL22V10 and easily test our
designs.

In some cases we might wish to supply continual clock pulses without
having to press the enter key.  For this we have the utility
XPLORCLK.EXE.  Enter the command line:

XPLORCNT n xxxx

where n is the LPT port number and xxxx are the number of milliseconds
we would like between clock pulses. This will supply a continuous stream
of clock pulses until we press a key. Use the value 1000 for the pulse
rate and you can watch the counters increment by one each second.

WRAPPING UP

The Programmable Logic Explorer is a great tool for learning about
programmable logic.  It gives you the ability the develop and test
designs in minutes.  It can also double as a ispGAL22V10 programmer. 
Next time we will take an in depth look at the 22V10 architecture and
it's capabilities. 


