Engineers will soon use 'virtual reality' to design computer chips

STANFORD, Calif.--March 22, 1995 -- Electrical engineers soon will be
forced to use "virtual reality" to design future generations of integrated
circuits.

Not only will such three-dimensional modeling become a necessity for
integrated circuit design, but it also will be required for making
optoelectronic devices, such as semiconductor lasers, and microscopic
machines, such as the tiny accelerometers that trigger airbag inflation in
today's automobiles.

Fortunately, the tools for doing this are not only feasible but practical,
Robert W. Dutton, professor of electrical engineering and chief scientist
at Stanford's Center for Integrated Systems (CIS), told scientists at the
annual meeting of the American Physical Society on March 21 in San Jose.

"The miniaturization of electrical devices, like the semiconductor
transistor, has reached the stage where two-dimensional simulations are no
longer adequate. But doing three-dimensional simulations of integrated
circuits is far more complicated than any of the computer graphics created
for Hollywood," Dutton said.

The key to performing such advanced modeling of the electrical properties
of integrated circuits is the ability to solve large numbers of special
equations called simultaneous partial differential equations. Three years
ago, CIS researchers received a "Grand Challenges" award in an
Intel-sponsored competition at the California Institute of Technology for
solving several million of these equations at a rate of more than 1.7
gigaFLOPS (1.7 billion floating point operations per second). To do so,
they used a custom-designed computer, called a parallel processor, that
cost tens of millions of dollars.

"It was something like proving that driving is possible with an automobile
that costs as much as a Rolls-Royce. It proved the feasibility, not the
practicality, of this approach," Dutton said.

Within the last few months, however, Stanford graduate student Bruce
Herndon, working with scientists at IBM, has developed a software
algorithm that allows even higher performance using commercial parallel
computers that cost about one-tenth as much as the custom machine used
just three years ago. The researchers have demonstrated the ability to
solve 1.5 million equations at 9.5 gigaFLOPS using IBM's new scaled
POWERparallel SP-2 system.

"This brings three-dimensional simulation capability down to a price that
semiconductor companies can afford. It also runs fast enough so that
designers can really use it. At these rates, 3-D will take about the same
time to run as current two-dimensional simulations," Dutton said.

In the past, engineers have designed integrated circuitry by relying on
vertical, two-dimensional simulations of individual transistors and the
other elements that make up typical microelectronic devices. But as these
elements have shrunk in size, width effects -- the interactions between
the electrons and the edge of devices -- have become increasingly
important. As a result, two-dimensional models have become less and less
representative. According to Dutton, the new equation-solving capability
will enable engineers to replace these two-dimensional simulations with
full three-dimensional analysis.

"Parallel computing promises nothing less than a revolution in the way
science and industry can now tackle large, complex problems," said Irving
Wladawsky-Berger, general manager of IBM's POWER Parallel Division. "The
exciting work at Stanford underscores the fact that high-performance
parallel systems can be incredibly cost effective, and that it's entirely
feasible to implement new applications with bold new visual and graphic
tools that can enhance perception and lead to important new insights."

The new equation-solving algorithm has been incorporated into a new version
of PISCES, a Stanford-written computer program that is commercially
available and simulates the behavior of the microscopic electronic
elements that are used for complex computer chips such as the PowerPC or
Pentium.

The code already has been restructured to run two-dimensional simulations
using parallel processors. It breaks down the millions of equations into a
number of smaller problems that are solved simultaneously by the
computer's multiple processors. As a result, the "parallelized" program
can solve these equations more rapidly than is possible with an ordinary
computer with only one processor.

Currently, Stanford and IBM researchers are working to extend the program's
capabilities to full, three-dimensional analysis by incorporating
techniques used in other experimental Stanford codes and IBM's well-known
3-D FIELDAY simulation code. At the same time, IBM has enlisted Stanford's
help in its effort to parallelize FIELDAY.

According to industry estimates, use of even two-dimensional simulations
can cut the cost of designing, testing and manufacturing a new computer
chip in half, and reduce development time by as much as a year. The
typical workstation that an integrated circuit designer uses has the
horsepower required to solve a few thousand differential equations
simultaneously, Dutton said. But even that can save millions of dollars
and increase the competitive advantage of the chip designers.

The capability to do three-dimensional modeling also may increase the rate
of innovation in the field. "There are some new technologies, like
sub-tenth-micron CMOS, silicon-on-insulator and silicon-germanium
technology, where we don't really capture all the behavior correctly in
2-D, so we really need 3-D modeling," said Ronald Knepper, an IBM
researcher visiting CIS who has been involved in the project.

Not only does this equation-solving capability apply to modeling
microelectronic devices, but it also can be applied to a number of other
areas, including fluid dynamics and genetic engineering.

Stanford University is offering the new parallel version of PISCES under a
non-exclusive license.

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