			Evaluation License
THE SOFTWARE AND ACCOMPANYING WRITTEN AND MAGNETIC MATERIALS ARE
PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND.  GREEN MOUNTAIN
COMPUTING SYSTEMS DOES NOT ACCEPT ANY RESPONSIBILITY FOR RESULTS
OBTAINED BY USING THIS SOFTWARE AND DOES NOT GUARANTEE THAT THE
SOFTWARE IS CORRECT.  YOU ARE ENTIRELY RESPONSIBLE FOR THE
RESULTS AND PERFORMANCE OF THE ACCOMPANYING SOFTWARE.  THIS LICENSE
GRANTS YOU THE RIGHT TO USE THIS ACCOMPANYING SOFTWARE FOR A LIMITED
TIME (30 DAYS) FOR EVALUATION PURPOSES ONLY.  YOU MAY NOT MAKE ANY
ATTEMPT TO DISASSEMBLE THE SOFTWARE.  THIS EVALUATION PACKAGE MAY
BE REDISTRIBUTED PROVIDED THAT IT IS DISTRIBUTED WITHOUT MODIFICATION,
AS A WHOLE, AND NO FEES ARE OBTAINED FROM SUCH DISTRIBUTION.

This is a description of the Green Mountain VHDL Educational Compiler and how
to use this demonstration version.

  You should have the following files:
	readme          This file
	order.frm       An order form to order the GM VHDL Compiler
	vhdl.exe        VHDL Compiler
	link.exe        VHDL Linker
	sv.exe          Text based simulation environment
	sve.exe         Graphically based simulation environment
	calc.vhd        An example VHDL design
	ieee.vhd        The IEEE Std_logic package
	ieee.o          The compiled IEEE Std_logic package
	vector.vhd      A bit_vector package
	vector.o        The compiled bit_vector package
	sve.fon         A font file for sve
	demo.bat        A batch file that demos the calc.vhd example

  Optionally you may obtain the gmdlx.zip file which contains a large
precompiled VHDL DLX processor model.  To try the compiler out quickly
type demo to run the demo.bat batch file.  This will compile, link, and
start the simulator for the example VHDL model in calc.vhd.

  The demonstration version includes a compiler, linker, and two loaders 
(simulation environments).  The compiler and linker produce an executable 
program for the 80386.  Since execution of a GM VHDL program requires a kernel,
the executable program must be run with a special loader that contains the 
kernel.  There are two royalty-free loaders in the package.  One of them 
simply loads your program, executes it, and returns to DOS.  In this case the 
only user interaction with the program is through your program's use of the 
Textio package.  The second loader loads your program and provides simulator-
like control of the kernel.  This allows you to run your program for small time
intervals, watch signals, and apply stimulus to signals.  It does not provide 
any single step debugging capabilities for processes.
  All of the software in the package uses a DOS extender written by Rational
Systems.  The DOS extender provides the GM VHDL compiler and your compiled 
programs with the benefit of 32-bit operation and virtual memory.  The section
on configuring the DOS extender will provide information about using 
virtual memory.

To compile and simulate a VHDL design type:

vhdl source_name
link bin_name obj_name entity_name [architecture_name]
sv time_value bin_name [configuration_name] 
OR
sve bin_name [configuration_name]

where source_name is the name of you VHDL design.  The vhdl program will create
an object file with the same name as your VHDL design only with a .o extension.
The link program reads this object file (obj_name) and creates an executable
simulation file (bin_name) of the an entity (entity_name) which was declared
in your VHDL design.  If an architecture name is supplied, a particular
architecture of the entity is used.  The default architecture is the last
one in the VHDL design file.  The sv and sve programs are used to execute
the compiled design.  The sv program takes as an argument the name of the
binary file created by the link program and a time value which is the amount
of time to simulate.  The sve program takes as an argument the name of the
binary file.  Both sv and sve optionally accept an argument that specifies the
name of a configuration file.  The following is a description of how to use
the configuration files.

  SimVHDL configuration files are text files used to setup SVE without
having to configure it each time through menus.  This can include configuring
a input signal of the entity being simulated to be forced to certain values
in a waveform file.  Waveform files are also text files that specify when an 
event occurs on an input signal.

  Configuration files are text files and contain one command, waveform 
specification, or comment per line.  They may be created with the edit program 
supplied with DOS.  A comment line is any line that begins with the \# 
character.  A waveform specification consists of the name of a signal followed
by at least one space or tab and the name of a waveform file to be associated 
with that signal.  The signal name may be a selected and/or indexed name as in 
GM VHDL.  The three commands available are view, step, and watch.  The view and
step commands begin with a parameter to the followed by at least one space 
or tab and the name of the command.  

  The watch command is the selected and/or indexed signal name followed by at least one space or tab and the command name watch.  The view command sets the 
size of the interval displayed in the trace window and its argument is a time 
value written as a decimal number followed by a unit name as specified in the 
predefined standard package.  The step command sets the duration of one 
simulation step.  This command also takes a time value, written as a decimal
number followed by a unit name, as an argument.  The watch command adds a 
signal to the list of signals being watched in the trace or watch windows.  
The argument to the watch command is the name of the signal.  The signal name 
may be a selected and/or indexed name as in GM VHDL.

An example configuration file might be:
100ns view
1ns step
in1 a.wav
in2 b.wav
out1 watch

This file sets the size of the trace window to be 100ns and the simulation step
to be 1ns.  The waveforms in the waveform files a.wav, and b.wav are associated
with signals in1 and in2.  The out1 signal will be added to either the trace
or watch window, depending on its type.

  Waveform files specify when an event should occur on an input signal and the
value to apply to the signal.  The waveform file is a text file and can be
created with the DOS edit program.  Each line of the file specifies one event
to be applied to the signal or an equation specifying a periodic event.  A
single event is specified by the time at which the event is to occur followed 
by at least one space or tab and an the value to apply.  The time value is the 
same as was described for configuration files.  A periodic event can be 
specified an equation of the form a+bx, where a and b are time values and x is 
the literal character x, followed by at least one space or tab and the value
to be applied.  The command will cause the event to occur at times a+bx, 
for x=0,1,2,3,...

For example, the file:
0ns 0
500ns+100ns x 0
550ns+100ns x 1

might be used to represent a clock that is initially zero, doesn't begin
running until time=500ns, has a 100ns cycle time and 50% duty cycle.

  The DOS environment variable VHDLPATH can be set to be a list of paths
that will be searched for any files required by any of these programs.
