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\ Filename: qsm332.f
\ Author: jack j. woehr jax@well.UUCP JAX on GEnie SYSOP, RCFB (303) 278-0364
\ Copyright (c) 1991, Vesta Technology, Inc.
\ ALL RIGHTS RESERVED.
\ Platform: SBC332 w/ VFSE
\ Purpose: Defines and primitives for SBC332 Queued Serial Modul (QSM)
\ Dependencies: Platform board; VFSE-332 operators W! W@ (16-bit ops).
\               Needs: YREG332.F
\ References: MC68332 USER'S MANUAL [MC68332UM/AD] Motorola, 1990
\ $Log:   V:/vestasrc/forth/68332/tpuqsm/vcs/qsm332.f_v  $
\ 
\    Rev 1.1   14 Jul 1992 11:26:26   jax
\ cleanup edits
\ 
\    Rev 1.0   17 Jun 1992 10:09:26   jax
\ Initial revision.

\
\ ** QSM registers and bits from MC68332UM/AD Tables 5-1 and 5-2.

BASE @
HEX
FFC00 YREG QMCR
    8000 CONSTANT QMCR.STOP
    4000 CONSTANT QMCR.FRZ1
    2000 CONSTANT QMCR.FRZ0
      80 CONSTANT QMCR.SUPV
      0F CONSTANT QMCR.IARB \ field, not bit mask

\ FFC02 YREG QTEST  \ Not used in VFSE-332
\      08 CONSTANT QTEST.TSBD
\      04 CONSTANT QTEST.SYNC
\      02 CONSTANT QTEST.TQSM
\      01 CONSTANT QTEST.TMM
    
FFC04 YREG QILR     \ 8 msbs
\ FFC05 YREG QILR     \ byte address, but SET-YREG uses W@ W!
    3800 CONSTANT QILR.ILQSPI   \ field
      0B CONSTANT >QILR.ILQSPI  \ bit shift
     700 CONSTANT QILR.ILSCI    \ field
      08 CONSTANT >QILR.ILSCI   \ bit shift
    
FFC04 YREG QIVR     \ 8 lsbs
      FF CONSTANT QIVR.INTV     \ number

\ FFC06 YREG RESERVED

FFC08 YREG SCCR0
    1FFF CONSTANT SCCR0.SCBR          \ field
    
FFC0A YREG SCCR1
    4000 CONSTANT SCCR1.LOOPS
    2000 CONSTANT SCCR1.WOMS
    1000 CONSTANT SCCR1.ILT
     800 CONSTANT SCCR1.PT
     400 CONSTANT SCCR1.PE
     200 CONSTANT SCCR1.M
     100 CONSTANT SCCR1.WAKE
      80 CONSTANT SCCR1.TIE
      40 CONSTANT SCCR1.TCIE
      20 CONSTANT SCCR1.RIE
      10 CONSTANT SCCR1.ILIE
       8 CONSTANT SCCR1.TE
       4 CONSTANT SCCR1.RE
       2 CONSTANT SCCR1.RWU
       1 CONSTANT SCCR1.SBK

FFC0C YREG SCSR
     100 CONSTANT SCSR.TDRE
      80 CONSTANT SCSR.TC
      40 CONSTANT SCSR.RDRF
      20 CONSTANT SCSR.RAF
      10 CONSTANT SCSR.IDLE
       8 CONSTANT SCSR.OR
       4 CONSTANT SCSR.NF
       2 CONSTANT SCSR.FE
       1 CONSTANT SCSR.PF

FFC0E YREG SCDR
     100 CONSTANT SCDR.R8/T8
      80 CONSTANT SCDR.R7/T7
      40 CONSTANT SCDR.R6/T6
      20 CONSTANT SCDR.R5/T5
      10 CONSTANT SCDR.R4/T4
       8 CONSTANT SCDR.R3/T3
       4 CONSTANT SCDR.R2/T2
       2 CONSTANT SCDR.R1/T1
       1 CONSTANT SCDR.R0/T0

\ FFC10 YREG RESERVED
\ FFC12 YREG RESERVED

FFC14 YREG QPDR     \ 8 lsbs only .. 8 msbs reserved
      80 CONSTANT QPDR.TXD
      40 CONSTANT QPDR.PCS3
      20 CONSTANT QPDR.PCS2
      10 CONSTANT QPDR.PCS1
       8 CONSTANT QPDR.PCS0/_SS
       4 CONSTANT QPDR.SCK
       2 CONSTANT QPDR.MOSI
       1 CONSTANT QPDR.MISO

FFC16 YREG QPAR     \ 8 msbs
\ FFC17 YREG QPAR   \ byte address, but SET-YREG uses W@ W!
    4000 CONSTANT QPAR.PCS3
    2000 CONSTANT QPAR.PCS2
    1000 CONSTANT QPAR.PCS1
     800 CONSTANT QPAR.PCS0/_SS
     200 CONSTANT QPAR.MOSI
     100 CONSTANT QPAR.MISO

FFC16 YREG QDDR     \ 8 lsbs
      80 CONSTANT QDDR.TXD
      40 CONSTANT QDDR.PCS3
      20 CONSTANT QDDR.PCS2
      10 CONSTANT QDDR.PCS1
       8 CONSTANT QDDR.PCS0/_SS
       4 CONSTANT QDDR.SCK
       2 CONSTANT QDDR.MOSI
       1 CONSTANT QDDR.MISO

FFC18 YREG SPCR0
    8000 CONSTANT SPCR0.MSTR
    4000 CONSTANT SPCR0.WOMQ
    3C00 CONSTANT SPCR0.BITS    \ field
      0A CONSTANT >SPCR0.BITS   \ shift
     200 CONSTANT SPCR0.CPOL
     100 CONSTANT SPCR0.CPHA
      FF CONSTANT SPCR0.SPBR    \ field

FFC1A YREG SPCR1
    8000 CONSTANT SPCR1.SPE
    7F00 CONSTANT SPCR1.DSCKL   \ field
      08 CONSTANT >SPCR1.DSCKL  \ shift
      FF CONSTANT SPCR1.DTL     \ field
    
FFC1C YREG SPCR2
    8000 CONSTANT SPCR2.SPIFIE
    4000 CONSTANT SPCR2.WREN
    2000 CONSTANT SPCR2.WRTO
     F00 CONSTANT SPCR2.ENDQP   \ field
      08 CONSTANT >SPCR2.ENDQP  \ shift
      0F CONSTANT SPCR2.NEWQP   \ field
      00 CONSTANT >SPCR2.NEWQP  \ shift

FFC1E YREG SPCR3    \ 8 msbs
\ FFC1F YREG SPCR3     \ byte address, but SET-YREG uses W@ W!
     400 CONSTANT SPCR3.LOOPQ
     200 CONSTANT SPCR3.HMIE
     100 CONSTANT SPCR3.HALT

FFC1E YREG SPSR     \ 8 lsbs
      80 CONSTANT SPSR.SPIF
      40 CONSTANT SPSR.MODF
      20 CONSTANT SPSR.HALTA
      0F CONSTANT SPSR.CPTQP   \ field

\ FFC20 YREG RESERVED       \ YFFC20 - YFFCFF

FFD00 YREG REC-RAM     \ YFFD00 - YFFD1F

FFD20 YREG TRAN-RAM    \ YFFD20 - YFFD3F

FFD40 YREG COMD-RAM         \ YFFD40 - YFFD4F
      80 CONSTANT COMD-RAM.CONT
      40 CONSTANT COMD-RAM.BITSE
      20 CONSTANT COMD-RAM.DT
      10 CONSTANT COMD-RAM.DSCK
      08 CONSTANT COMD-RAM.PCS3
      04 CONSTANT COMD-RAM.PCS2
      02 CONSTANT COMD-RAM.PCS1
      01 CONSTANT COMD-RAM.PCS0/_SS

\ ** QSM Functionality

\ *** [MC68332UM/AD 5.4.2.1]

\ TRUE stops, FALSE enables QSM. Supervisor mode only.
: QSM-STOP ( flag --)
    QMCR.STOP QMCR ROT SET-YREG ;
\ To avoid complications at restart & prevent data corruption,
\ first disable all submodules: SCI rx/tx should be disabled, and
\ operation completion verified before asserting STOP. QSPI submodule
\ should be stopped by asserting SPCR3.HALT and asserting STOP after
\ HALTA flag set.

\ TRUE causes QSM to HALT on transfer boundary when FREEZE asserted
\ on IMB, FALSE causes QSM to ignore said signal. FREEZE is asserted
\ when 332 enters the background mode.
: QSM-FREEZE ( flag --)
    QMCR.FRZ1 QMCR ROT SET-YREG ;

\ TRUE sets QSM supervisor-only access, FALSE (from supervisor mode,
\ of course, resets to QSM user access permitted.
: QSM-SUPERVISOR ( flag --)
    QMCR.SUPV QMCR ROT SET-YREG ;

\ 0 causes 332 to view QSM int as spurious, 1 (lo) to 15 (hi) are
\ interrupt arbitration priority levels.
: QSM-IARB! ( 0-15 --)
    QMCR.IARB AND           \ acceptable values 0 - 15
    QMCR W@                 \ fetch reg contents
    QMCR.IARB INVERT AND    \ mask off IARB bits
    OR                      \ OR in desired mask
    QMCR W!                 \ store reg
;

\ *** [MC68332UM/AD 5.4.2.2] is for when MCU is in test mode.
\ Not used in Vesta Forth Standard Edition

\ *** [MC68332UM/AD 5.4.2.3]
\ Int levels 0-7; if same, QSPI given priority.
: QSM-INT-LEVEL ( QSPI-level SCI-level --)
    >QILR.ILSCI LSHIFT QILR.ILSCI AND       \ shift 0-7 mask and constrain
    SWAP
    >QILR.ILQSPI LSHIFT QILR.ILQSPI AND     \ ditto
    OR                                      \ form combination desired mask
    QILR W@                                 \ get register
    QILR.ILQSPI QILR.ILSCI OR INVERT AND    \ mask off IL fields from reg
    OR                                      \ OR in desired mask
    QILR W!                                 \ store reg
;

\ *** [MC68332UM/AD 5.4.2.4]
\ Int vectors for QSPI/SCI are adjacent; bit D0 of int vect is 0 for SCI
\ and 1 for QSPI.
: QSM-INT-VECTOR ( vector --)
    QIVR.INTV AND QIVR W! ;

\ *** [MC68332UM/AD 5.4.3]
\ In general, bit assignments can be handled directly by the application
\ using SET-YREG from YREGS322.F


BASE !
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