New Tool verifies IEEE 1149.1 compliance and test programs with logic
simulation

Los Altos, CA, 1 February, 1994 ... Alpine Image Systems, Inc. (AIS) has
introduced a new test pattern generation tool set for logic simulation.
The AVLsim Tool Kit uses logic simulation to verify that JTAG hardware has
been implemented in a way that makes the circuit scan testable. The tool
assists design engineers in the evaluation of the scan-related (IEEE Std
1149.1-1990) portions of a design and is well suited for both chip and
board level simulation environments, then the logic simulator can be used
to generate test vectors automatically. That means test programs can be
written, and debugged before real hardware exists.

AVLsim generates stimulus patterns for use with all popular logic
simulation tools. It can be used with any logic simulator that accepts
tabular stimulus from a text file, including tools from Mentor Graphics,
Compass, Viewlogic, Cadence, and Orcad to name a few. It is also suitable
for use with hardware simulators and emulators from Quickturn, Pi, IKOS
and Zycad. "AVLsim will let designers confirm the correct functionality of
their parts much earlier in the design cycle" said Ellis Goldberg, the AIS
Director of Marketing.

Chip designers will use AVLsim to test the functionality of the 1149.1 test
access port (TAP), internal scan for fault simulation, build-in self-test
(BIST) and boundary scan operation. When the vectors generated by AVLsim
are applied with traditional simulation vectors the interaction of scan
and non-scan logic can be observed.

Programs developed for simulation using AVLsim are 100% compatible with
AIS's proTEST series of PC-based boundary scan testers, preserving the
investment made in test development during design verification for later
use in hardware debug, manufacturing test and field service. "The
re-usability of test programs is the only paradigm that makes economic
sense in today's market. Test engineering departments can no longer afford
to re-develop tests from scratch." Mr Goldberg added. (SEE DIAGRAM)

The DOS version of AVLsim Tool Set is available immediately, priced from
$6,000 for a single seat license. The AVLsim Tool Set generates test
programs that can later be run on the proTEST Boundary Scan Test System
priced from $7995. Delivery is 30 to 60 days. Prices are US domestic
prices and will be higher outside the US. 

AIS, 821 Riverside Drive, Los Altos, CA 94024
(415) 941-3247, (415) 941-7642 FAX

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