ADVER MULTIFUNCTIONAL UTILITY FOR PORTFOLIO ASIC DESIGN LIBRARY PORTED TO
PCS RUNNING WINDOWS

Cross Platform Support Between PCs and Workstations Leads Trend to
Outsource Easy to Use Third-Party Design Tools Over Creation In-House.

Sunnyvale, CA -- March 20, 1995 - Aspec Technology, Inc., the leading
supplier of ASICWare design technology and automation (DTA) for personal
computer and microelectronics industries, said that its Adver PC (Aspec
Design Verifier) multifunctional DTA utility is now available for
DOS-based personal computers and workstations running Microsoft Windows
operating systems.

Adver functions within Aspec's proprietary Portfolio family of DTA tools as
the primary communication link between Portfolio, the user and the
semiconductor manufacturer. Adver provides the precise timing requirements
needed to design complex circuits in the most advanced technologies while
being compatible with third party CAE design tools.

Adver's new porting allows an easy transfer between platforms and widens
platform selection to enable low-cost front end design on PCs running
Windows, and to easily interface with all popular third-party routing
tools on workstations at the back-end (layout) of the design process.
Target users are those users of ViewLogic simulators, Intergraph synthesis
and simulation and other PC platform-based ftone-end design tools
Originally developed for UNIX environments, the new Adver is available
now, including one process-selectable library, at a single-quantity price
of $7,500 for Microsoft Windows NT and $5,000 for Microsoft Windows.

'Outsourcing libraries -- and DTA tools in general -- is a major trend
today This parallels the trend in the mid-1980's to outsourcing of CAE
design tools Aspec DTA tools, including libraries, provide a proven
risk-free, turnkey design solution for both array and cell-based circuits,
reducing design and manufacturing costs,' said Conrad Dell'Oca, Aspec's
president and CEO 'With many manufacturing processes supported worldwide,
Aspec is well-positioned for the next industry evolution.'

Adver rapidly and accurately calculates pin-to-pin delays, translates
netlists from one format to another, back annotates from layout, and
checks logical design rules Adver also calculates the pre- and post-layout
pin-to-pin delays necessary for accurate design simulations Delay
calculation is based on a 4x4 matrix, and timing models take into account
rise and fall times and output loading, interconnect parasitics, plus
voltage, temperature and process design variations. All this ensures fully
functional devices that perform correctly the first time Adver is the
'gateway' to the success of Aspec's Works Right The First Time design
methodology. Technically, it assures the extra level of accuracy for delay
timing and signoff quality.

The utility provides an easy-to-use pop-up menu screen to facilitate data
entry. Adver fully supports popular third-party simulation environments
from Mentor, Cadence, Viewlogic, Intergraph, Ikos and Zycad for signoff,
as well as array and cell layout tools from Arcsys, Cadence and Silicon
Valley Research environments. Adver is also fully compatible with a dozen
Aspec-qualified silicon suppliers (Samsung, Sanyo, Thesys
Microelectronics, Hyundai and others) In addition, Adver assists the user
to rapidly retarget circuits from one qualified supplier to another.

Adver reads and writes several different types of netlist formats (Verilog,
EDIF, TDL, etc ), and generates pre-layout and post-layout delay
calculation files for all operating conditions for back annotation. For
design violation checking, dozens of different logic rules are checked
against the netlist; violations are flagged, and a report summarizing
violations is generated Other pertinent design information is also
provided, such as gate count, I/O count, cell types used and pins per
net.

Adver extracts timing information from the selected semiconductor
manufacturer's technology libraries, from the design's place and route
database, and derates according to user-specified operating conditions in
order to calculate pre- and post-layout delays. Adver calculates the
delays for custom masterslices or embedded memories from the Portfolio
library compilers, and can be run in a batch mode as well as interactive
mode.

ASPEC'S PORTFOLIO PRODUCT FAMILY

The licensing of Aspec's Portfolio design tools provides designers with a
turnkey design capability including all methodology, technology libraries,
software, compilers and megacells necessary to design low-cost proprietary
structured custom circuits (ASICs and ASSPs) from a standard, reliable
architecture using advanced tool- and foundry-independent technology
Portfolio provides the ability to create ASIC designs without having to
select in advance the target foundry User designs can then be
multiple-sourced and produced by third-party silicon suppliers, all with
rapid design and production turnaround at lower cost.

HDA/HDEA/HDC TECHNOLOGY

Aspec's product line and services are built upon its proprietary Sea of
Gates HDA, HDEA (embedded) and HDC (cell) architecture, which
significantly increases the densities of arrays and standard cells over
competing architectures HDA/HDEA/HDC technology features densities of over
two million available gates using 0.5-micron process, with even smaller
geometries under development
Design flexibility is a major technology feature, as well as the speed of
design completion, lower power dissipation, reduced chip costs and easy
technology migration. Because of inherent time-to-market and low cost
attributes, the technology already has had a significant impact on the PC
and electronics industry Aspec gate arrays and cells have been designed
into over 200 high-volume personal computer, electronic system and other
digital signal processing, consumer and appliance applications.

Aspec Technology, Inc., has now signed strategic manufacturing agreements
with a half-dozen leading semiconductor manufacturers in its quest to
establish its HDA technology as the ASIC industry worldwide standard. The
entry of Aspec and its manufacturing partners in the ASIC market creates a
new ASIC power with an aggregated revenue rank in the top ten ASIC
suppliers It is estimated that total design and production bookings for
the group (based on Aspec's technology) exceeded $200 million in calendar
1994 Estimated bookings for 1995 are over $400 million.

Aspec is a fast-growing, privately company that has been profitable since
its founding in late 1991. Founders and top management are executive
alumni of major Silicon Valley companies Aspec is located at 830 East
Arques Ave, Sunnyvale, CA 94086, telephone 408/774-2199, fax 408/522-9450

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